The present invention relates to a power circuit of SMPS (Switching Mode Power Supply) and more particularly to a phase-difference synchronization controlling circuit of a power circuit which operates two or more SMPSs in parallel.
Generally, when circuits having different operation output voltage levels are operated in parallel, one or more power supplies should be operated in parallel with respect to one input.
To operate two circuits being respectively supplied with a power source of different levels, two power supplies are used. For example, SMPS operated with at least two or more power circuits having a PWM (pulse width modulation) device is used.
When two power circuits are operated in parallel within a SMPS having two or more power circuits, new higher harmonics are generated by the power source switching frequency difference between two power circuits, thereby affecting the operation of the power circuit.
To prevent generation of higher harmonics due to the switching frequency difference of two power circuits during parallel-operation of two power circuits, the method of phase-synchronizing the outputs of the PWM pulse generators in the respective insides of the two power circuits is used. The circuit for this method is described in FIG. 1.
FIG. 1 is a conventional parallel power circuit diagram of SMPS, which comprises a power source filter 10 for removing noise included in an input DC supply voltage Vdc and outputting the noise-removed voltage, a first controller 14 for outputting a predetermined PWM pulse having a predetermined period and a clock synchronized to the PWM pulse, in response to an input of a DC voltage Vdc outputted from the power source filter 10, a second PWM controller 16 for generating a predetermined PWM pulse having a predetermined period in response to an input of the DC voltage, and outputting the generated PWM pulse with being phase-synchronized to a clock outputted from the first PWM controller 14, first and second transformers 18 and 20 whose one-sided ends of primary windings n11 and n21 are connected to the supply voltage Vdc, for induced-outputting the voltage inputted to the primary windings n11 and n21 to respective secondary windings n12 and n22, first and second switching transistors 22 and 24 coupled between the other terminals of the primary windings n11 and n21 of the first and second transformers 18 and 20, for driving the first and second transformers 18 and 20 by being switched with the PWM pulses respectively outputted from the first and second PWM controllers 14 and 16, and rectifying portions 26 and 28 for rectifying and outputting the pulse voltages outputted from the respective secondary windings n12 and n22 of the first and second transformers 18 and 20.
The first and second PWM controllers 14 and 16 in the constitution of FIG. 1 are connected to components of resistor and capacitor for determining an internal oscillation time constant.
FIGS. 2A to 2C are operational waveform diagrams for explaining the operation of FIG. 1, in which FIGS. 2A and 2B are waveform diagrams of currents flowing in the primary windings n11 and n21 of the first and second transformers 18 and 20, and FIG. 2C is a current waveform diagram of the input supply voltage Vdc when the first and second transformers 18 and 20 are driven as shown in FIGS. 2A and 2B.
If a DC voltage Vdc is now supplied to the circuit of FIG. 1, the input filter 10 removes a noise of the input supply voltage Vdc, which is supplied to one-sided terminals of the respective primary windings n11 and n21 of the first and second transformers 18 and 20 and to the power lines 32 and 34 of the first and second PWM controllers 14 and 16.
At this time, the first PWM controller 14 supplies the predetermined PWM pulse 37 through the line 36 to the base of the transistor 22 and at the same time, supplies a clock having the same period as that of the outputted PWM pulse 37 through the line 30 to the second PWM controller 16, in response to an input of the voltage Vdc outputted from the filter 10.
Meanwhile, the second PWM controller 16 generates a PWM pulse of a predetermined time constant in response to the input of the supply voltage Vdc outputted from the filter 10, and synchronizes the generated PWM pulse to the clock inputted through the line 30 and outputs the PWM pulse 39 generated in its inside to the line 38. Accordingly, the second PWM controller 16 outputs the PWM pulse synchronized to the clock outputted from the first PWM controller 14, so that the PWM pulses 37 and 39 outputted from the first and second PWM controllers 14 and 16 are outputted with the same frequency.
The first and second transistors 22 and 24 for receiving the PWM pulses 37 and 39 respectively outputted from the first and second PWM controllers 14 and 16 in their base terminals through the lines 36 and 38 are switched according to input periods of the PWM pulses 37 and 39.
If the first and second transistors 22 and 24 are switched "on", the current of the supply voltage Vdc received in one-sided terminals of the primary windings n11 and n21 of the first and second transformers 18 and 20 flows through the respective collector-emitter. That is, if the two transistors 22 and 24 are switched "on", respective current loops of primary windings n11 and n21 of the first and second transformers 18 and 20 are formed, thereby respectively flowing currents i1 and i2.
At this time, if it is assumed that the PWM pulses 36 and 38 respectively outputted from the first and second PWM controllers 14 and 16 have frequencies having the same phase, and an on/off duty ratio is 50%, the currents i1 and i2 respectively flowing in the primary windings n11 and n21 of the first and second transformers 18 and 20 become those of FIGS. 2A and 2B.
Accordingly, in the SMPS having the above constitution shown in FIG. 1, the two power circuits are operated with the same frequency as described above, thereby preventing higher harmonics generated in parallel operation of two SMPSs.
However, because the frequencies of PWM pulses outputted from the first and second PWM controllers 14 and 16 are equal, currents of the primary windings respectively flow in the primary windings of the first and second transformers 18 and 20 at the same time, so that the circuit in FIG. 1 should be supplied with a DC input as much as the amount of summed current.
That is, since the phases of the PWM pulses outputted from the two PWM controllers 14 and 16 are equal, the current I, i.e., a sum i1+i2 of currents i1 and i2 flowing in the primary windings n11 and n21 of the first and second transformers 18 and 20 as shown in FIG. 2C should be supplied to the input filter 10.
Accordingly, the power circuit of FIG. 1 generates a problem in that the power supplier for supplying a DC supply voltage Vdc shown in FIG. 1 should have large capacity because of an increase in currents consumed in the two transformers 18 and 20.